数字设计和计算机体系结构

《数字设计和计算机体系结构(英文版第2版)》基于作者哈里斯丰富的教学和实践经验，以幽默的写作风格展示了最新的数字设计技术。书中采用一种独特的现代数字设计方法，先介绍数字逻辑门，接着讲述组合电路和时序电路的设计，并以这些基本的数字逻辑设计概念为基础，重点介绍如何设计实际的MIPS处理器。另外，在全书的实例中运用SystemVerilog和VHDL展示基于CAD的电路设计方法和技术。通过本书，读者能够构建自己的微处理器，并能够自顶向下地理解微处理器的工作原理。
《数字设计和计算机体系结构(英文版第2版)》更新了关于微机上通用处理器以及几乎随处可见的微控制器中的I/O系统的内容，提供了多个实例来说明如何使用RS232、SPI、电机控制、中断、无线和模数转换器与外围设备交互。除了对全书内容进行更新和扩展外。新版在编程和代码例题中采用SystemVerilog(替代Verilog)与VHDL一起给出数字系统设计的实现。第2版还提供了更多的练习题。来加强编程与处理器体系结构之间的联系。

In Praise of Digital Design and Computer Architecture
Preface
About the Authors
Chapter 1 From Zero to One
1.1 The Game Plan
1.2 The Art of Managing Complexity
1.2.1 Abstraction
1.2.2 Discipline
1.2.3 The Three-Y's
1.3 The Digital Abstraction
1.4 Number Systems
1.4.1 Decimal Numbers
1.4.2 Binary Numbers
1.4.3 Hexadecimal Numbers
1.4.4 Bytes, Nibbles, and All That Jazz
1.4.5 Binary Addition
1.4.6 Signed Binary Numbers
1.5 Logic Gates
1.5.1 NOT Gate
1.5.2 Buffer
1.5.3 AND Gate
1.5.4 OR Gate
1.5.5 Other Two-Input Gates
1.5.6 Multiple-Input Gates
1.6 Beneath the Digital Abstraction
1.6.1 Supply Voltage
1.6.2 Logic Levels
1.6.3 Noise Margins
1.6.4 DC Transfer Characteristics
1.6.5 The Static Discipline
1.7 CMOS Transistors
1.7.1 Semiconductors
1.7.2 Diodes
1.7.3 Capacitors
1.7.4 nMOS and pMOS Transistors
1.7.5 CMOS NOT Gate
1.7.6 Other CMOS Logic Gates
1.7.7 Transmission Gates
1.7.8 Pseudo-nMOS Logic
1.8 Power Consumption
1.9 Summary and a Look'Ahead
Exercises
Interview Questions
Chapter 2 Combinational Logic Design
2.1 Introduction
2.2 Boolean Equations
2.2.1 Terminology
2.2.2 Sum-of-Products Form
2.2.3 Product-of-Sums Form
2.3 Boolean Algebra
2.3.1 Axioms
2.3.2 Theorems of One Variable
2.3.3 Theorems of Several Variables
2.3.4 The Truth Behind It All
2.3.5 Simplifying Equations
2.4 From Logic to Gates
2.5 Multilevel Combinational Logic
2.5.1 Hardware Reduction
2.5.2 Bubble Pushing
2.6 X's and Z's, Oh My
2.6.1 Illegal Value: X
2.6.2 Floating Value: Z
2.7 Karnaugh Maps
2.7.1 Circular Thinking
2.7.2 Logic Minimization with K-Maps
2.7.3 Don't Cares
2.7.4 The Big Picture
2.8 Combinational Building Blocks
2.8.1 Multiplexers
2.8.2 Decoders
2.9 Timing
2.9.1 Propagation and Contamination Delay
2.9.2 Glitches
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