"刘汉诚（John H. Lau），伊利诺伊大学香槟分校理论与应用力学博士，不列颠哥伦比亚大学结构工程硕士，威斯康星大学麦迪逊分校工程力学硕士，菲尔莱狄更斯大学管理科学硕士，台湾大学土木工程学士。
历任台湾欣兴电子股份有限公司CTO、香港ASM太平洋科技有限公司高级技术顾问、台湾工业技术研究院研究员、香港科技大学客座教授、新加坡微电子研究院MMC实验室主任、惠普实验室/安捷伦公司资深科学家（超过25年）。
拥有40多年的集成电路研发和制造经验，专业领域包括集成电路的设计、分析、材料、工艺、制造、认证、可靠性、测试和热管理等，目前研究领域为芯片异构集成、SiP、TSV、扇出/扇入晶圆/面板级封装、MEMS、mini/ micro LED、3D IC集成、SMT和焊接力学等。
发表480多篇论文，发明30多项专利，举办 300多场讲座，撰写20多部教科书（涉及3D IC 集成、TSV、优选 MEMS 封装、倒装芯片 WLP、面积阵列封装、高密度 PCB、SMT、DCA、无铅材料、焊接、制造和可靠性等领域）。
ASME Fellow、IEEE life Fellow、IMAPS Fellow，积极参与ASME、IEEE和IMAPS的多项技术活动。获得ASME、IEEE、SME等协会颁发的多项荣誉，包括IEEE/ECTC很好会议论文（1989)、IEEE/EPTC很好论文奖(2009)、ASME Transactions很好论文奖(电子封装杂志，2000)、IEEE Transactions很好论文奖(CPMT，2010)、ASME/EEP杰出技术成就奖(1998)、IEEE/CPMT电子制造技术奖(1994)、IEEE/CPMT杰出技术成就奖(2000)、IEEE/CPMT杰出持续技术贡献奖（2010）、SME电子制造全面很好奖（2001）、潘文渊杰出研究奖（2011）、IEEE 继续教育杰出成就奖（2000）、IEEE CPMT技术领域奖（2013）和 ASME 伍斯特·里德·华纳奖章（2015）等。
"
目录
Preface
1 3D Integration for Semiconductor IC Packaging
1.1 Introduction
1.2 3D Integration
1.3 3D IC Packaging
1.4 3D Si Integration
1.5 3D IC Integration
1.5.1 Hybrid Memory Cube
1.5.2 Wide I/O DRAM and Wide I/O 2
1.5.3 High Bandwidth Memory
1.5.4 Wide I/O Memory (or Logic-on-Logic)
1.5.5 Passive Interposer (2.5D IC Integration)
1.6 Supply Chains before the TSV Era
1.6.1 FEOL (Front-End-of-Line)
1.6.2 BEOL (Back-End-of-Line)
1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)
1.7 Supply Chains for the TSV Era-Who Makes the TSV
1.7.1 TSVs Fabricated by the Via-First Process
1.7.2 TSVs Fabricated by the Via-Middle Process
1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process
1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process
1.7.5 How About the Passive TSV Interposers
1.7.6 Who Wants to Fabricate the TSV for Passive Interposers
1.7.7 Summary and Recommendations
1.8 Supply Chains for the TSV Era-Who Does the MEOL, Assembly, and Test
1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process
1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process
1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process
1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers
1.8.5 Summary and Recommendations
1.9 CMOS Images Sensors with TSVs
1.9.1 Toshiba's DynastronTM
1.9.2 STMicroelectronics' VGA CIS Camera Module
1.9.3 Samsung's S5K4E5YX BSI CIS
1.9.4 Toshiba's HEW4 BSI TCM5103PL
1.9.5 Nemotek's CIS
1.9.6 SONY's ISX014 Stacked Camera Sensor
1.10 MEMS with TSVs
1.10.1 STMicroelectronics’ MEMS Inertial Sensors
1.10.2 Discera's MEME Resonator
1.10.3 Avago's FBAR MEMS Filter
1.11 References
2 Through-Silicon Vias Modeling and Testing
2.1 Introduction
2.2 Electrical Modeling of TSVs
2.2.1 Analytic Model and Equations for a Generic TSV Structure
2.2.2 Verification of the Proposed TSV Model in Frequency Domain
2.2.3 Verification of the Proposed TSV Model in Time Domain
2.2.4 TSV Electrical Design Guideline
2.2.5 Summary and Recommendations
2.3 Thermal Modeling of TSVs
2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction
2.3.2 Thermal Behavior of a TSV Cell
2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations
2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations
2.3.5 Summary and Recommendations
2.4 Mechanical Modeling and Testing of TSVs
2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si
2.4.2 Experimental Results on Cu Pumping during Manufacturing
2.4.3 Cu Pumping under Thermal Shock Cycling
2.4.4 Keep-Out-Zone of Cu-Filled TSVs
2.4.5 Summary and Recommendations
2.5 References
3 Stress Sensors for Thin-Wafer Handling and Strength Measurement
4 Package Substrate Technologies
5 Microbumps: Fabrication, Assembly, and Reliability
6 3D Si Integration
7 2.5D/3D IC Integration
8 3D IC Integration with Passive Interposer
9 Thermal Management of 2.5D/3D IC Integration
10 Embedded 3D Hybrid Integration
11 3D LED and IC Integration
12 3D MEMS and IC Integration
13 3D CMOS Image Sensor and IC Integration
14 3D IC Packaging
Index
